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Extra resources for Advances in Solid State Circuits Technologies
1998], pseudo differential stages [Gharbiya & Syrzycki, 2002], and shift level biasing [Wang & Guggenbuhl, 1990]. Source degeneration using resistors or MOS transistors is the simplest method to linearize transconductor. However, it requires a large resistor to achieve a wide linear input range. In addition, MOS used as resistor exhibits considerable varitions affected by process and temperture and results in the linearity degradation. Crossing-coupling with multiple differential pairs is designed only for the balanced input signals.
A. (1997). A high-speed median circuit. IEEE J. Solid-State Circuits, vol. 32, June 1997, pp. 905-908. Semiconductor Industry Association. (2008). International technology roadmap for semiconductors 2008 update. [Online]. net/. ; Taylor, J. & Wilby, M. (1995). A scalable high-speed current mode winner-takeall network for VLSI neural applications. IEEE Trans. Circuits Syst. I, Fundam. , vol. 42, no. 5, 1995, pp. 289–291. A. & Fang, X. (1993). CMOS current mode winner-take-all circuit with both excitatory and inhibitory feedback.
2004). A 4-MHz CMOS continuous-time filter with on-chip automatic tuning, IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, (Jun 2004) pp. ; R. G. Carvajal R. ; Lopez-Martin A. & Carlosena A. (2004). A novel low-voltage low-power class-AB linear transconductor, IEEE Proceedings of International Sympoisum of Circuits and Systems, Vol. 1, pp. 725-728, ISBN 0-7803-8251-X, Vancouver, British Columbia, Canada, May 2004, Institute of Electrical and Electronics Engineers, Piscataway Lee S. ; Park S.